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E. Zanoni  - - - 
Top co-authors See all
Gaudenzio Meneghesso

258 shared publications

Department of Information Engineering, University of Padova, 35131 Padova, Italy

Matteo Meneghini

256 shared publications

Department of Information Engineering, University of Padova, 35131 Padova, Italy

A. Castaldini

135 shared publications

Crystal Growth Laboratory, Universidad Autonoma de Madrid, Madrid Spain

Alessandro Chini

84 shared publications

University of Modena and Reggio Emilia, Modena, Italy

Piero Olivo

84 shared publications

Department of Engineering, University of Ferrara, Ferrara, Italy

242
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Publication Record
Distribution of Articles published per year 
(1993 - 2018)
Total number of journals
published in
 
20
 
Publications See all
Article 0 Reads 0 Citations Evaluation of novel carrier substrates for high reliability and integrated GaN devices in a 200 mm complementary metal–o... S. Stoffels, K. Geens, X. Li, D. Wellekens, S. You, M. Zhao,... Published: 17 September 2018
MRS Communications, doi: 10.1557/mrc.2018.192
DOI See at publisher website
Article 0 Reads 0 Citations Failure limits and electro-optical characteristics of GaN-based LEDs under electrical overstress N. Renso, M. Buffolo, C. De Santi, M. Ronzani, G. Meneghesso... Published: 01 September 2018
Microelectronics Reliability, doi: 10.1016/j.microrel.2018.06.054
DOI See at publisher website
Article 0 Reads 0 Citations Degradation mechanisms of heterogeneous III-V/Silicon loop-mirror laser diodes for photonic integrated circuits M. Buffolo, M. Pietrobon, C. De Santi, F. Samparisi, M.L. Da... Published: 01 September 2018
Microelectronics Reliability, doi: 10.1016/j.microrel.2018.06.058
DOI See at publisher website
Article 0 Reads 0 Citations Impact of sidewall etching on the dynamic performance of GaN-on-Si E-mode transistors A. Tajalli, E. Canato, A. Nardo, M. Meneghini, A. Stockman, ... Published: 01 September 2018
Microelectronics Reliability, doi: 10.1016/j.microrel.2018.06.037
DOI See at publisher website ABS Show/hide abstract
The aim of this paper is to investigate the role of the etching of the sidewalls of p-GaN on the dynamic performance of normally-off GaN HEMTs with p-type gate. We analyze two wafers having identical epitaxy but with different recipes for the sidewall etching, referred to as “Etch A” (non-optimized) and “Etch B” (optimized). We demonstrate the following relevant results: (i) the devices with non-optimized etching (Etch A), when submitted to positive gate bias, show a negative threshold voltage shift and a decrease in Ron, which are ascribed to hole injection under the gate and/or in the access regions; (ii) transient characterization indicates the existence of two trap states, with activation energies of 0.84 eV (CN defects) and 0.30 eV. The latter (with time-constants in the ms range) is indicative of the hole de-trapping process, possibly related to trap states in the AlGaN barrier or at the passivation/AlGaN interface; (iii) by optimizing the p-GaN sidewall etching (for the same epitaxy) it is possible to completely eliminate the threshold voltage shift. This indicates that hole injection mostly takes place along the sidewalls.
Article 0 Reads 0 Citations Impact of dislocations on DLTS spectra and degradation of InGaN-based laser diodes D. Monti, M. Meneghini, C. De Santi, A. Bojarska, P. Perlin,... Published: 01 September 2018
Microelectronics Reliability, doi: 10.1016/j.microrel.2018.06.055
DOI See at publisher website
Article 1 Read 0 Citations Current induced degradation study on state of the art DUV LEDs N. Trivellin, D. Monti, C. De Santi, M. Buffolo, G. Meneghes... Published: 01 September 2018
Microelectronics Reliability, doi: 10.1016/j.microrel.2018.07.145
DOI See at publisher website
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